The present disclosure relates generally to integrated circuit device design, and more specifically, to a layout for a field effect transistor (FET) device with a multi-finger gate structure and multiple source/drain regions.
Multi-fingered field effect transistors (FETs) are widely used in various integrated circuit applications. Multi-finger transistor layouts are widely used in CMOS circuit designs. Compared with single-finger transistor layout, its main features include effectiveness in reducing circuit physical size, reducing gate resistance (and thus improve the RF performance of the FET), and improving device matching. There is a need to make each finger's source node voltage the same for all fingers and also to make each finger's drain node voltage the same for all fingers. Namely, there exists a need to reduce cross-finger electric variations of the multi-finger FET device.
In conventional multi-finger transistor layouts, electric currents passing through individual finger transistors are not the same. More specifically, there are more drain current and more gate leakage current in an outer finger than those in an inner finger. In other words, when going from an outer finger to an inner finger, there is a systematic variation in each finger's electric current. Additionally, for a given drain breakdown voltage of a given FET type, prior-art multi-finger layout cannot fully utilize available drain breakdown voltage.